Embodiments of the present invention relate to asemiconductor device and a semiconductorsystem including the same, and more particularly to a technology for reducing a toggle current of a global input output (GIO) of a semiconductor device configured to use a data bus inversion (DBI) scheme.
Along with the increasing degree of integration found in semiconductor memory devices, the semiconductor memory devices have also been continuously improved to increase the operation speed. In order to increase operation speeds of the semiconductor memory devices, synchronous memory devices capable of operating by synchronizing with an external clock of a memory chip have been recently proposed and developed.
A representative example of thesynchronous memory device is a single data rate (SDR) synchronous memory device that is synchronized with a rising edge of an external clock of a memory device such that one data piece can be input and/or output at one data pin during one period of the clock.
However, the SDR synchronous memory device may experience difficulty in satisfying a high-speed operation of the system. In order to solve such a problem facing the SDR synchronous memory device as so described, a double data rate (DDR) synchronous memory device capable of processing two data pieces during one clock period has been proposed.
Two contiguous data pieces are input and output through respective data input/output (I/O) pins of the DDR synchronous memory device, such that the two contiguous data pieces are synchronized with a rising edge and a falling edge of an external input clock. Therefore, although a clock frequency of the DDR synchronous memory device is not increased, the DDR synchronous memory device, as described here, may have a bandwidth that is at least two times larger than that of the SDR synchronous memory device. Accordingly, the DDR synchronous memory device can operate at a higher speed than the SDR synchronous memory device.
The DDR synchronous memory device is configured to use a multi-bit prefetching scheme capable of simultaneously processing multiple bits (multi-bit) of data pieces. The multi-bit prefetch scheme synchronizes sequentially input data pieces with a data strobe signal such that the input data pieces can be arranged in parallel to one another. Thereafter, the multi-bit prefetch scheme can simultaneously store the arranged multi-bit data pieces upon receiving a write command synchronized with an external clock signal.
The semiconductor memory device may be configured to store or output data in response to a command requested by a chipset. That is, if a data write operation is requested by the chipset, data entered through an input pad is stored in memory cells. If a data read operation is requested by the chipset, data stored in memory cells is externally output through an output pad.
Generally, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) includes a variety of circuits to perform a variety of operations. The Joint Electron Device Engineering Council (JEDEC) serves as a semiconductor standardization organization and has set forth standardized operations and circuits of semiconductor devices. Further, the semiconductor devices, as so described, must be designed on the basis of the JEDEC specification.
With the increasing development of fabrication and design technologies of semiconductor devices, the operation speed of the semiconductor devices is rapidly increasing. The semiconductor devices have been sequentially developed in the order of DDR2→DDR3→DDR4 according to operation speeds thereof. As the semiconductor devices have been sequentially developed in the order of DDR2→DDR3→DDR4, conventional circuits may disappear from use in the semiconductor devices. Alternatively, circuits needed for new operations may be added as necessary. Such circuits and the associated circuit operations have been defined in various other specifications.
For example, Cyclic Redundancy Checks (CRC) associated specifications and command/address parity associated specifications have been added to DDR4. In addition, Data Bus Inversion (DBI) associated specifications and new parameters have been added. The semiconductor device must perform operations corresponding to such specifications. Further, the semiconductor device must include circuits designed tocorrespond to the operations.
LPDDR4 receives data through a data bus during a write operation mode and loads the received data on a global input/output (GIO) line. However, assuming that data of the GIO line transitions several times by the data bus inversion (DBI) scheme, an unnecessary toggle current may be generated by the semiconductor device.
Specifically, the write driver according to the conventional art may be configured to reflect data inversion information into data. In this case, data inversion is performed once in the write driver. Next, such a data inversion is performed once more in a local input/output (I/O) line driver. As a result, data of the GIO line is unnecessarily transitioned several times, resulting in increase of unnecessary current consumption.